1. Field of the Invention
This invention relates in general to a synchronization circuit for electronic devices and components and more specifically to a synchronization circuit capable of operating in a master and a slave mode. One embodiment of the invention relates to a synchronization circuit for electronic devices and components, the circuit being of the type which comprises an internal synchronization signal generator and an input/output terminal whereat an external synchronization signal can be received, or the internal synchronization signal can be supplied from the circuit.
Another embodiment of the invention also concerns a method of generating and supplying a synchronization signal to a plurality of electronic devices being operated as slave devices to a synchronization circuit acting as the master device, and wherein the synchronization circuit can, in turn, be operated in the slave mode to receive an external synchronization signal.
2. Discussion of the Related Art
Many applications require in the electronic industry that a number of electronic devices from the same circuit family, or from families of some different type, be rendered compatible with one another. This means that the devices should be capable of operating at the same working frequency to avoid the occurrence of intermodulation phenomena.
This requirement is usually met by using a special synchronization circuit which enables one of the devices to act as the master device, while the other active devices operate in the slave mode.
In essence, one of the devices--referred to as the master--functions as a synchronization circuit and impresses a synchronization signal clock which is picked up by all the slave devices to time their synchronization signals.
A good synchronization circuit should be able to receive or supply the synchronization signal at/to a single output node, but should not form its synchronization signal at that node when operated in the slave mode.
One known synchronization circuit is shown in FIG. 1. In the example of FIG. 1, a synchronization circuit 10 includes a squaring or clipping circuit 11 connected after an oscillator 12. An input terminal IN of the oscillator 12 is supplied an enable signal OSC which is also supplied in parallel to the input of an ON/OFF switch 13. The ON/OFF switch 13 has an output which is coupled to activate the oscillator 12. The switch 13 can be regarded as being part of the synchronization circuit 10.
The clipper 11 is effective to clip the saw-toothed signal output by the oscillator 12. The output of the clipper 11 is connected to a circuit node U supplying a synchronization signal SINC to other circuit components, which are generally designated 14 and internal to the circuit 10.
The synchronization circuit 10 may be operated in a master mode. In master mode, the circuit 10 may supply the signal SINC to electronic devices connected to the terminal A. Alternatively, the circuit 10 may be operated in slave mode, whereby the signal SINC is received at the node U over a connection 15 from the terminal A connected to the output of another master device, not shown in the figure.
In other words, when operating in slave mode, no saw-toothed signal is generated, and the synchronization signal SINC is delivered from outside, i.e. from the terminal A.
The input terminal IN is utilized for controlling the master or slave mode of the synchronization circuit, where a capacitor or a resistor is connected toward ground outside the oscillator. Both the capacitor and the resistor would normally be provided to form an RC circuit.
The known synchronization circuit of FIG. 1 has, however, the following drawbacks. First, a second terminal must be made available for controlling the synchronization circuit. In addition, because the saw-toothed signal is not generated when operating in the slave mode the circuit 10 cannot be used in many applications to which that signal is essential, including Pulse Width Modulators.
A second prior art synchronization circuit is illustrated in FIG. 2 wherein the components already mentioned in connection with FIG. 1 are denoted by the same reference numerals.
The circuit of FIG. 2 can be implemented without a control terminal because the saw-toothed signal from the oscillator is controlled through the synchronization signal SINC alone. In fact, upon detection of the synchronization signal, the saw-toothed signal will be forced to discharge. The receipt of the first input the synchronization signal will also force the outputting of its synchronization signal at node U, as generated by the clipper 11, after a predetermined time delay Td, where the time delay Td is due to the delays of the oscillator 12 and the clipper 11. One problem associated with the circuit of FIG. 2 is that when the two synchronization signals have equal duration, the delay Td of the slave synchronization circuit will cause the synchronization signal to expand, thereby lowering the oscillation frequency. In addition, consumption is bound to increase due to the master circuit clipper tending to force the terminal to discharge, but meeting the opposition of the clipper incorporated to the slave which can deliver a larger current than the master can accept.
If the duration of the synchronization signal of the slave is longer than that of the master, the frequency is further reduced and consumption increased accordingly. Where several devices are to be synchronized, these problems become more serious as a result of the propagation delays introduced by the length of the layout connections.
Plots illustrating the status of the SINC signals versus time are shown in FIGS. 3A and 3B, where FIG. 3A illustrates an ideal synchronization and FIG. 3B illustrates a real synchronization. In FIGS. 3A and 3B, SINC is the synchronization signal, and I (SINC) is the current flowing through the terminal to which the signal SINC is applied.
An additional problem with the circuit of FIG. 2 is that if the synchronization pulse is a very short one, it may be depleted by the time the slave synchronization signal arrives. In this case, the slave would turn into master and force a synchronization signal to the real master, causing the signal to bounce from one circuit to another and the system oscillation frequency to rise until the inverse of the propagation time Td. This phenomenon is illustrated in FIG. 4, which shows the pattern of a synchronization signal whose period is equal to Td.
It would be desirable to provide a synchronization circuit and synchronization method which have such constructional and functional features that would overcome the limitations and drawbacks mentioned above in connection with the background art.